1. Field of the Invention
This invention relates to semiconductor fabrication and, in particular, to an improved method for creating a mask pattern of an integrated circuit (IC) for use in lithographic processing.
2. Description of Related Art
Integrated circuits are fabricated by lithographic techniques, where energy beams transmit integrated circuit images or patterns on photomasks to photosensitive resists on semiconductor wafer substrates. The circuit image on the photomask may not be reproduced precisely on the substrate, in part because of optical effects among transmitted and blocked energy passing through the photomask.
Optical Proximity Correction (OPC) has been employed as a key enabling resolution enhancement technique required to meet image size control requirements imposed by state-of-the-art integrated circuit product programs. OPC is essentially the deliberate and proactive distortion of photomask patterns to compensate for systematic and stable errors. OPC is generally categorized as either rules-based or model-based. Rules-based OPC is done by determining the correctable imaging errors, calculating appropriate photomask compensations, and finally applying the calculated corrections directly to the photomask layout. While proven to be very efficient at correcting some important one- and two-dimensional imaging problems, non-iterative rules-based OPC is generally believed limited in its usefulness due to the finite number of rules that are available to describe all layout situations, the difficulty of calculating exact correction values based on measured errors, and the lack of feedback loop during the correction process.
Existing model-based OPC tools overcome some of these shortcomings by employing an essentially trial-and-error iterative optimization approach. Model-based OPC is based on the concept of capturing the imaging characteristics in a mathematical model, or a combination of mathematics and heuristics, and calculating only the expected on-wafer circuit image which would be projected by the mask pattern under investigation. The correction to be applied is never directly calculated. Rather, the correction is derived by comparing the simulated image contour placement to the edge placement of the original mask pattern and iteratively adjusting until a match is found or until all iterations are exhausted.
For example, as shown in FIG. 1a, the actual circuit pattern to be reproduced on a substrate layer is created on a mask. An existing OPC tool then runs a simulation on these patterns and predicts the actual wafer pattern image after transmission onto the wafer substrate, taking into account optical proximity effects, as shown in FIG. 1b. The OPC tool then compares the wafer image FIG. 1b with the original circuit pattern FIG. 1a, determines the required adjustment of the mask pattern so that the mask and wafer images are in better agreement. After a first pass correction and movement of edges that do not agree, a new mask image is then created, FIG. 1c. The OPC tool again runs a simulation of the mask pattern image which will be created on the wafer substrate, and generates a new predicted wafer image, FIG. 1d. The process continues if necessary with a subsequent correction to create a new mask image, FIG. 1e, and another simulation of the pattern image created on the wafer, FIG. 1f. Typically the OPC process takes up to eight to ten, or more, iterations until a suitable mask image is created. By basing the correction on a layout independent model of the patterning process and iterating toward an optimized correction, model-based OPC overcomes many of the shortcomings of rules-based OPC outlined above.
The goal of any resolution enhancement technique (RET) ultimately should be to improve circuit performance or yield. In order to do so, RET has to ensure the layout patterns are replicated within the specifications assumed by the circuit designer over the largest possible process window (i.e., range of exposure dose and defocus). Although they have improved pattern replication on wafers, present rules-based and model-based OPC methods still present deficiencies in producing circuit pattern in that their goal is to improve accuracy of pattern replication at one point of the process window (i.e., one dose and focus) rather than optimizing dimensional control over the entire process window (i.e., a large range of dose and focus).
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved method to implement model-based optical proximity correction to circuit patterns on photolithography masks.
It is another object of the present invention to provide a proximity correction technique that improves circuit performance or yield by increasing the process window over which acceptable line width tolerances can be maintained.
A further object of the invention is to provide a proximity correction technique that optimizes overlap between achievable dimensional bounds and acceptable target dimensional bounds.
It is yet another object of the invention to provide a proximity correction technique that recognizes the fact that conditions in an IC manufacturing process fluctuate and that chip designs function over a finite range of dimensional variations.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.
The target dimensional bounds of the pattern may be established by determining maximum variations in pattern edge placement which still provide adequate pattern feature performance, and the simulated achievable dimensional bounds of the pattern may be established by determining optical proximity effects of the feature pattern on the mask during lithographic production. In general, the simulated achievable dimensional bounds of the pattern may be established by determining lithographic process variations during lithographic production, for example, by determining variations in lithographic dosage through the mask during lithographic production, by determining variations in lithographic focus through the mask during lithographic production, or by determining variations in etching during lithographic production.
The method preferably further includes modifying lithographic process conditions to reduce the locations where the simulated achievable dimensional bounds of the pattern exceed the target dimensional bounds of the pattern. Lithographic process conditions may be reviewed to ensure that widths of the simulated achievable dimensional bounds are narrower than widths of target dimensional bounds for corresponding portions of the feature pattern. The mask feature pattern may be modified to reduce the locations where the simulated achievable dimensional bounds of the pattern exceed the target dimensional bounds of the pattern. More preferably, the mask feature pattern is modified to ensure that the simulated achievable dimensional bounds are within the target dimensional bounds for the feature pattern.
The target dimensional bounds may be determined from theoretical design rules, or from empirical experimental data. The simulated achievable dimensional bounds may be determined from first principle modeling, or from empirical measurements. The target dimensional bounds and simulated achievable dimensional bounds may be represented by a band showing ranges of feature edges, or by lines showing maximum and minimum feature edges. Determining the locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern may include calculating total area of the simulated achievable dimensional bounds outside of the acceptable target dimensional bounds. Where the target dimensional bounds and simulated achievable dimensional bounds are represented by pixels, calculating total area of the simulated achievable dimensional bounds outside of the acceptable target dimensional bounds may be accomplished by determining the sum of all pixels outside of the acceptable target dimensional bounds.
In another aspect, the present invention provides a method of creating a pattern for a mask adapted for use in lithographic production of integrated circuits on a semiconductor substrate, wherein the method comprises providing a mask pattern of a feature to be created on the semiconductor substrate using the mask, and modifying lithography process exposure dose and focus conditions and/or the mask pattern to maximize the usable range of exposure dose and focus conditions in the lithographic production.
In a further aspect, the present invention provides a method of creating a pattern for a mask adapted for use in lithographic production of integrated circuits on a semiconductor substrate, wherein the method comprises providing a mask pattern of a feature to be created on the semiconductor substrate using the mask, establishing target dimensional bounds of the pattern, and modifying the mask pattern such that the resulting image of the mask pattern created on the semiconductor substrate falls within the target dimensional bounds of the pattern.
Yet another aspect of the present invention provides a method of creating a pattern for a mask adapted for use in lithographic production of integrated circuits on a semiconductor substrate, wherein the method comprises providing a mask pattern of a feature to be created on the semiconductor substrate using the mask, determining simulated achievable dimensional bounds of the pattern, and modifying the mask pattern such that the resulting image of the mask pattern created on the semiconductor substrate falls within the simulated achievable dimensional bounds of the pattern.
A related aspect of the present invention provides a computer program product for creating a pattern for a mask adapted for use in lithographic production of integrated circuits on a semiconductor substrate, the mask pattern being of a feature to be created on the substrate using the mask. The computer program product has computer readable program code means for establishing target dimensional bounds of the pattern, computer readable program code means for; determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and computer readable program code means for determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern.
Another related aspect of the present invention provides a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for creating a pattern for a mask adapted for use in lithographic production of integrated circuits on a semiconductor substrate, the mask pattern being of a feature to be created on the substrate using the mask. The method steps comprise establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern.